“The next discoveries made with the CERN LHC will be triggered by one Columbia chip and measured by another.” Columbia Engineering features a nice overview article (pdf)) of our collaboration with the Columbia ATLAS Group at the Nevis Laboratories designing two high performance, radiation-hard ADCs for the ATLAS experiment in the Large Hadron Collider (LHC) at CERN. It has been an honor to collaborate with John Parsons, Gustaaf Brooijmans, Jaro Ban, Tim Andeen, Nan Sun, and many others. The ’numbers’ of this experiment are mind boggling: the tunnel is 27km long, the particles race at 99.999999% of the speed of light in bunches with a bunch-crossing rate of 40MHz, creating about 1 billion collisions per second. The detector is several stories high and has more than 180,000 channels, requiring two ADCs. For the next LHC upgrade starting in 2026, more than 45,000 of our 8-channel ADC chips will be installed. ...

Matt Venn from TinyTapeout and Zero to ASIC Course interviewed me about MOSbius. Matt asked interesting questions and the live demos worked great! Go watch the video including the demo of a first-order delta-sigma modulator with MOSbius and leave a comment. Matt’s LinkedIn Post

Posted on LinkedIn: It was a humbling but deeply gratifying experience to receive a Presidential Award for Outstanding Teaching at the Columbia University Commencement today. Many thanks for everyone who helped me get here. Thanks to my family for their patience and support, my teachers and mentors, my students for their feedback and interest, my TAs for their help and dedication, my colleagues and EE support staff, our industrial sponsors, and a special thank you to Yannis Tsividis for his example and mentorship on striving for teaching excellence. ...

The Electrical Engineering Department and the School of Engineering and Applied Science did a profile on my teaching. Enjoy the article (pdf)

Posted on LinkedIn: It was an honor and true pleasure to present the MOSbius circuit lab educational platform as the keynote luncheon at the IEEE Custom Integrated Circuits Conference If you are interested to try out MOSbius in your courses, don’t hesitate to contact me – contact info is on https://mosbius.org. We have sample kits available and are ramping up to make more kits for labs in the fall semester. ...

Proud to present my new website developed with Hugo and hosted on GitHub Pages and discuss here how I built the site. How did I build this website? NOTE: I am not trying to write a full tutorial, there are (too) many already out there. I am outlining how I went about building this website and I am documenting some things I had to learn the hard way, i.e. lost too much time for something that was relatively simple in hindsight but I just did not find it easily in the existing tutorials. ...

Posted on LinkedIn: Want to offer your students hands-on labs in your integrated-circuits courses connecting measurement, simulation, and analysis? We created the MOSbius chip for that purpose! Documentation and example experiments are available at https://mosbius.org. The 68-pin MOSbius chip contains nMOS and pMOS devices as individual transistors, and in typical configurations like current mirrors, differential pairs, common-source configuration, simple operational transconductance amplifiers or inverters. Circuits can be built with external wires and there is also a 65x10 on-chip digitally controlled switch matrix than can connect each of the 63 transistor-terminal pins and the VDD and VSS to 10 buses on the chip to build circuits. ...

Posted on LinkedIn: Chips are working! Well-deserved kudos to the “VLSI Design Lab” (t/o course) students who measured their chips and demonstrated them in an application. Take a look at their websites and videos. We had another successful VLSI Design Lab offering at Columbia in 2024. Students designed custom chips from scratch in spring, taped them out to a commercial foundry in summer, tested them, and demonstrated them in fall in an application with their custom PCB: three PPG chips: a PPG with SpO2 measurement, a PPG with heart-rate and breathing-rate measurement, and a low-power PPG with lock-in amplification; an ECG chip including a 10-bit SAR ADC; an AM radio with upconversion to a 10.7MHz IF; a light-powered potentiostat; an ultra-low-power R-C sensor readout; an NPU accelerator for CNNs; and last but not least, a full RISC-V processor. ...

Posted on LinkedIn: We taped-out our 2024 VLSI Design Lab class projects!! Three PPG chips, an ECG chip, an AM radio, a potentiostat, a sensor readout, a radar baseband, an NPU and last but not least, a RISC-V processor have been sent out for fabrication. Congratulations to all teams for completing their tape-out and many thanks to the teaching assistants Berk ADIM, Mor Shimshi, Alfred Festus Davidson and Zhipeng Fan for all their help and tireless mentorship. Many thanks to Mingoo Seok for co-supervising the RISC-V design. ...

Posted on LinkedIn: Hot of the press in the SSCS Magazine Summer 2023: “Teaching IC Design: From Concepts to Testing a Fabricated Custom Chip” Sharing my experience with teaching a design lab class where students conceive, design, lay-out, send out for fabrication, and then test their own chip. If you have any questions, don’t hesitate to contact me. Full article: – make sure to read the acknowledgments, none of this would have been possible without the help of many others. ...